In a synchronous DRAM device, the time delay for generating output data in response to a read command received in synchronization with a clock is generally equal to a CAS latency (CL) times a clock period (tCK) plus an access time (tAC). Here, the CAS latency is generally an integer multiple or a half integer multiple of the clock period tCK. However, as the scale of integrated circuits and systems become larger, the delay time associated with the output of data in a synchronous DRAM must be carefully and variably controlled. In particular, in a system containing a DRAM controller and a plurality of synchronous DRAM devices electrically coupled thereto, it would preferable if the delay time associated with the output of data from each DRAM device could be independently controlled to inhibit the likelihood of simultaneous arrival of large quantities of data at the DRAM controller.
To provide independent control of the delay time, integrated circuit delay lines have been proposed. In an integrated circuit delay line which can be programmed, coarse programmable delay and fine programmable delay can typically be separately controlled. The coarse programmable delay is typically an integer or one-half integer multiple of the period T of an input clock CLK, and the fine programmable delay is less than an integer or one-half integer multiple of the period T. An exemplary delay line is disclosed in an article by Y. Okajima et al. entitled "Digital Delay Locked Loop and Design Technique for High-Speed Synchronous Interface", IEICE Trans. Electron., Vol. E79-C, No. 6, pp. 798-807, June (1996). Unfortunately, the timing of the coarse and fine delays may be influenced by changes in operating voltage, temperature and process variations. Thus, there continues to be a need for integrated circuit delay lines having improved characteristics.